Scaling and other advances in silicon (Si) technology have brought about compact, high-performance SiGe bipolar and CMOS transistors and various RF, microwave, and mm-wave circuits implemented in Si technology. Si is an ideal technology for implementing an entire electronic system, as the various components of the system (e.g., digital, analog, memory, and RF components) can be integrated on a single substrate or chip. One bottleneck for Si-based, single-chip design in many applications is the implementation of a high-performance power amplifier.
While the feasibility of Si-based power amplifiers on a Si substrate has recently been demonstrated, commercially available designs provide relatively low output power and low-efficiency performance (“efficiency” being defined herein as the ratio of RF output power to the direct-current (DC) power dissipated by the circuit). The relatively poor performance of Si-based power amplifiers has been attributed to an inherent trade-off between the speed of a Si transistor and its breakdown voltages. As a result of this trade-off, high-speed Si transistors optimized for RF and microwave applications have relatively low breakdown voltages (e.g., ranging from about 1.2V to several volts). The output swing voltage of a Si power transistor is typically limited by the low breakdown voltage of the transistor, requiring an increase in the output signal current in order to boost the output power. Traditionally, the design of Si-based power amplifiers has been accomplished using wide transistors driven at very high currents. Parallel combinations of large transistors and power-combining architectures have also typically been necessary to boost the output power of the amplifier.
Some power amplifier designs relying on series-stacked transistors have been proposed. For example, J. Jeong et al., “A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs,” 16 IEEE Microwave & Wireless Components Letters 684-686 (2006), the entire disclosure of which is expressly incorporated herein by reference, describes the use of stacked transistors in Silicon-on-Sapphire (SOS) and Silicon-on-Insulator (SOI) technologies to boost the output swing voltage and output impedance. S. Pornpromlikit et al., “A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS,” 58 IEEE Transactions on Microwave Theory & Techniques 57-64 (2010), the entire disclosure of which is expressly incorporated herein by reference, describes a similar approach. As explained in those references, the gate of each transistor is biased at a fixed voltage, and the voltage swings are therefore limited by the gate oxide breakdown. This limitation prevents stacking more than four transistors and/or applying large bias voltages.
U.S. Pat. No. 6,888,396 to A. Hajimiri et al. (Hajimiri), the entire disclosure of which is expressly incorporated herein by reference, presents several designs for stacking field-effect transistors (FET) and bipolar transistors to construct multi-cascode cells. The majority of the circuit designs described in Hajimiri are fixed gate-bias topologies and suffer from the drawbacks of gate oxide breakdown described above. The design presented in FIG. 9 of Hajimiri utilizes transformer coupling to overcome gate oxide breakdown but does not allow biasing of the gate-source of individual transistors (thus, resulting in low efficiency and precluding use in linear power amplifiers). The circuit design shown in FIG. 7 of Hajimiri, on the other hand, requires diodes that are not readily available in standard bulk and silicon-on-insulator (SOI) CMOS integrated circuit processes (thus, defeating the goal of a single substrate, without resort to a BiCMOS process).
The use of feedback resistors for the self-biasing of stacked FETs and bipolar transistors (in order to boost the output voltage of the amplifier) is described in J. G. McRory et al., “Transformer Coupled Stacked FET Power Amplifiers,” 34 IEEE J. Solid-State Circuits 157-161 (1999), M. Lei et al., “Design and Analysis of Stacked Power Amplifier in Series-Input and Series-Output Configuration,” 55 IEEE Transactions on Microwave Theory & Techniques 2802-2812 (2007), and U.S. Patent Publication No. 2009/0115529 to S. Chao et al., the entire disclosures of which are each expressly incorporated herein by reference. In theory, this approach protects the stacked structure from both source-drain reach-through and gate oxide breakdown under high voltage swings. In practice, however, introducing feedback resistors results in instability, particularly when the number of stacked transistors increases (thereby increasing the positive feedback signal). Thus, these designs are also limited to a maximum of four stacked transistors for optimum performance.